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ae5314a6bf
With this commit, the RV30 and RV40 decoders no longer clobber the fpu state for normal decoding (only error resilience can still do so). rv34_idct_add_c: 58.1 ( 1.00x) rv34_idct_add_mmxext: 16.5 ( 3.52x) rv34_idct_add_ssse3: 12.2 ( 4.76x) Reviewed-by: Lynne <dev@lynne.ee> Signed-off-by: Andreas Rheinhardt <andreas.rheinhardt@outlook.com>
164 lines
4.8 KiB
NASM
164 lines
4.8 KiB
NASM
;******************************************************************************
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;* ASM-optimized functions for the RV30 and RV40 decoders
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;* Copyright (C) 2012 Christophe Gisquet <christophe.gisquet@gmail.com>
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;*
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;* This file is part of FFmpeg.
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;*
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;* FFmpeg is free software; you can redistribute it and/or
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;* modify it under the terms of the GNU Lesser General Public
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;* License as published by the Free Software Foundation; either
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;* version 2.1 of the License, or (at your option) any later version.
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;*
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;* FFmpeg is distributed in the hope that it will be useful,
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;* but WITHOUT ANY WARRANTY; without even the implied warranty of
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;* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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;* Lesser General Public License for more details.
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;*
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;* You should have received a copy of the GNU Lesser General Public
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;* License along with FFmpeg; if not, write to the Free Software
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;* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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;******************************************************************************
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%include "libavutil/x86/x86util.asm"
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SECTION_RODATA
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; 0 1 2 3 (words) -> 1 3 2 0 1 3 2 0 (words)
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shuffle: times 2 db 2, 3, 6, 7, 4, 5, 0, 1
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pw_13: times 8 dw 13
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pw_17: times 8 dw 17
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pw_7: times 8 dw 7
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pw_col_coeffs: dw -17, -7, -13, 13, 7, -17, 13, 13
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pd_512: times 4 dd 0x200
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SECTION .text
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%macro IDCT_DC_NOROUND 1
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imul %1, 13*13*3
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sar %1, 11
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%endmacro
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%macro IDCT_DC_ROUND 1
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imul %1, 13*13
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add %1, 0x200
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sar %1, 10
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%endmacro
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INIT_XMM sse2
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cglobal rv34_idct_dc_noround, 1, 2, 1
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movsx r1, word [r0]
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IDCT_DC_NOROUND r1
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movd m0, r1d
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SPLATW m0, m0
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mova [r0+ 0], m0
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mova [r0+16], m0
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RET
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%macro COL_TRANSFORM 3
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; -17*c1-7*c3 | 13*c0-13*c2 | 7*c1-17*c3 | 13*c1+13*c2 = -z3 | z1 | z2 | z0
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pmaddwd %2, m7
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movd m3, %1
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pshufd %3, %2, q0123 ; z0 | z2 | z1 | -z3
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psignd %2, m7 ; z3 | z1 |-z2 | z0
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paddd %3, m5
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paddd %2, %3 ; z0+z3 | z1+z2 | z1-z2 | z0-z3 (+round)
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%ifidn %3,m1
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pxor m1, m1
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%endif
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psrad %2, 10
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punpcklbw m3, m1
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packssdw %2, %2
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paddw %2, m3
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packuswb %2, %2
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movd %1, %2
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%endmacro
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INIT_XMM ssse3
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; ff_rv34_idct_add_ssse3(uint8_t *dst, ptrdiff_t stride, int16_t *block)
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cglobal rv34_idct_add, 3, 3, 8, dst, stride, block
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; row transform
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movq m0, [blockq + 0*8]
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movq m1, [blockq + 1*8]
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movq m2, [blockq + 2*8]
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movq m3, [blockq + 3*8]
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pxor m7, m7
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mova m6, [shuffle]
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mova [blockq + 0], m7
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mova [blockq + 16], m7
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mova m4, m0
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mova m5, [pw_13]
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paddsw m0, m2 ; b0 + b2
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pshufb m1, m6
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psubsw m4, m2 ; b0 - b2
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pmullw m0, m5 ; *13 = z0
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pshufb m3, m6
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pmullw m4, m5 ; *13 = z1
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mova m5, m1
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pmullw m1, [pw_17] ; b1*17
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pmullw m5, [pw_7] ; b1* 7
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pshufb m0, m6
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mova m2, m3
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pmullw m3, [pw_17] ; b3*17
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pmullw m2, [pw_7] ; b3* 7
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pshufb m4, m6
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mova m7, [pw_col_coeffs]
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paddsw m1, m2 ; z3 = b1*17 + b3* 7
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psubsw m5, m3 ; z2 = b1* 7 - b3*17
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mova m2, m0
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mova m6, m4
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paddsw m0, m1 ; z0 + z3
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paddsw m4, m5 ; z1 + z2
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psubsw m2, m1 ; z0 - z3
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psubsw m6, m5 ; z1 - z2
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mova m5, [pd_512] ; 0x200
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COL_TRANSFORM [dstq], m0, m1
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COL_TRANSFORM [dstq+strideq], m4, m0
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lea dstq, [dstq + 2*strideq]
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COL_TRANSFORM [dstq], m6, m0
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COL_TRANSFORM [dstq+strideq], m2, m0
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RET
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; ff_rv34_idct_dc_add_sse4(uint8_t *dst, int stride, int dc);
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%macro RV34_IDCT_DC_ADD 0
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cglobal rv34_idct_dc_add, 3, 3, 6
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; load data
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IDCT_DC_ROUND r2
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pxor m1, m1
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; calculate DC
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movd m0, r2d
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lea r2, [r0+r1*2]
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movd m2, [r0]
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movd m3, [r0+r1]
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pshuflw m0, m0, 0
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movd m4, [r2]
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movd m5, [r2+r1]
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punpcklqdq m0, m0
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punpckldq m2, m3
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punpckldq m4, m5
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punpcklbw m2, m1
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punpcklbw m4, m1
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paddw m2, m0
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paddw m4, m0
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packuswb m2, m4
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movd [r0], m2
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%if cpuflag(sse4)
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pextrd [r0+r1], m2, 1
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pextrd [r2], m2, 2
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pextrd [r2+r1], m2, 3
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%else
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psrldq m2, 4
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movd [r0+r1], m2
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psrldq m2, 4
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movd [r2], m2
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psrldq m2, 4
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movd [r2+r1], m2
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%endif
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RET
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%endmacro
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INIT_XMM sse2
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RV34_IDCT_DC_ADD
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INIT_XMM sse4
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RV34_IDCT_DC_ADD
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